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FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
September 2006
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Features
12 x 9 Crosspoint Matrix Supports SD, PS, and HD 1080i/1080p Video Input Clamp / Bias Circuitry AC or DC-Coupled Inputs AC or DC-Coupled Outputs Dual-Load (75) Output Drivers with High-Impedance
Description
The FMS6501 switch matrix provides flexible options for today's video applications. The 12 inputs that can be routed to any of nine outputs. Each input can be routed to one or more outputs, but only one input may be routed to any one output. The input to output routing is controlled via an I2CTM-compatible digital interface. Each input supports an integrated clamp option to set the output sync tip level of video with sync to ~300mV. Alternatively, the input may be internally biased to center signals without sync (Chroma, Pb, Pr) at ~1.25V. These DC output levels are for the 6dB gain setting. Higher gain settings increase the DC output levels accordingly. The input clamp / bias mode is selected via I2C. Unused outputs may be powered down to reduce power dissipation.
Disable One-to-One or One-to-Many Input to Output Switching Programmable Gain: +6, +7, +8, or +9dB I2CTM Compatible Digital Interface, Standard Mode 3.3V or 5V Single-Supply Operation Lead-Free SSOP-28 Package
Applications
Cable and Satellite Set-Top Boxes TV and HDTV Sets A/V Switchers Personal Video Recorders (PVR) Security / Surveillance Video Distribution Automotive (In-Cabin Entertainment)
Ordering Information
Part Number
FMS6501MSA28 FMS6501MSA28X
Pb-Free
Yes Yes
Temperature Range
0C to 85C 0C to 85C
Package
SSOP-28 SSOP-28
Container
Rail Reel
Quantity
47 2000
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
www.fairchildsemi.com
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Block Diagram
IN1 C/B
IN2
C/B
IN12
C/B
SDA SCL ADDR VCC (2) GND (2) OUT1 OUT2 OUT9 Programmable Enable/Disable Programmable Gain 6, 7, 8, or 9dB
Figure 1. FMS6501 Block Diagram
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
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FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Pin Configuration
IN1 IN2 IN3 IN4 IN5 IN6 VCC GND IN7 IN8 IN9 IN10 IN11 IN12
1 2 3 4 5 6 28 27 26 25
Pin Assignments
Pin#
OUT1
Name
IN1 IN2 IN3 IN4 IN5 IN6 VCC GND IN7 IN8 IN9 IN10 IN11 IN12 ADDR SCL SDA OUT9 OUT8 OUT7 GNDO VCCO OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
Type
Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Input Input Output Output Output Output Output Output
Description
Input, channel 1 Input, channel 2 Input, channel 3 Input, channel 4 Input, channel 5 Input, channel 6 Positive power supply Must be tied to ground Input, channel 7 Input, channel 8 Input, channel 9 Input, channel 10 Input, channel 11 Input, channel 12 Selects I2C address. "0" = 0x06 (0000 0110), `1" = 0x86 (1000 0110) Serial clock for I2C port Serial data for I2C port Output, channel 9 Output, channel 8 Output, channel 7 Must be tied to ground Positive power supply for output drivers Output, channel 6 Output, channel 5 Output, channel 4 Output, channel 3 Output, channel 2 Output, channel 1
1
OUT2 OUT3 OUT4 OUT5 OUT6 VCCO GNDO OUT7 OUT8
2 3 4 5 6 7 8 9 10 11 12
FAIRCHILD FMS6501
24 23
28L SSOP
7 8 9 10 11 12 13 14 22 21 20 19 18 17 16 15
OUT9 SDA SCL ADDR
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Figure 2. Pin Configuration
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
www.fairchildsemi.com 3
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Absolute Maximum Ratings
The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table defines the conditions for actual device operation.
Parameter
DC Supply Voltage Analog and Digital I/O Output Current Any One Channel, Do Not Exceed
Min.
-0.3 -0.3
Max.
6.0 Vcc + 0.3 40
Unit
V V mA
Reliability Information
Symbol
TJ TSTG TL JA Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 seconds) Thermal Resistance, JEDEC Standard Multilayer Test Board, Still Air 50 -65
Parameter
Min.
Typ.
Max.
150 150 300
Unit
C C C C/W
Recommended Operating Conditions
Symbol
TA VCC Supply Voltage Range
Parameter
Operating Temperature Range
Min.
0 3.135
Typ.
5.000
Max.
85 5.250
Unit
C V
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
www.fairchildsemi.com 4
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Digital Interface
The I2C-compatible interface is used to program output enables, input to output routing, input clamp / bias, and output gain. The I2C address of the FMS6501 is 0x06 (0000 0110) with the ability to offset it to 0x86 (1000 0110) by tying the ADDR pin high. Both data and address data, of eight bits each, are written to the I2C address to access all the control functions. There are separate internal addresses for each output. Each output's address includes bits to select an input channel, adjust the output gain, and enable or disable the output amplifier. More than one output can select the same input channel for one-to-many routing. When the outputs are disabled, they are placed in a high-impedance state. This allows multiple FMS6501 devices to be paralleled to create a larger switch matrix. Typical output power-up time is less than 500ns. The clamp / bias control bits are written to their own internal address, since they should always remain the same regardless of signal routing. They are set based on the input signal connected to the FMS6501. All undefined addresses may be written without effect.
Output Control Register Contents and Defaults Control Name
Enable Gain Inx
Width
1 bit 2 bits 5 bits
Type
Write Write Write
Default
0 0 0
Bit(s)
7 6:5 4:0
Description
Channel Enable: 1=Enable, 0=Power Down(1) Channel Gain: 00=6dB, 01=7dB, 10=8dB, 11=9dB Input selected to drive this output: 00000=OFF(2), 00001=IN1, 00010=IN2... 01100=IN12
Notes: 1. Power down places the output in a high-impedance state so multiple FMS6501 devices may be paralleled. Power down also de-selects any input routed to the specified output. 2. When all inputs are OFF, the amplifier input is tied to approximately 150mV and the output goes to approximately 300mV with the 6dB gain setting.
Output Control Register MAP Register Register Name Address Bit 7
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 Enable Enable Enable Enable Enable Enable Enable Enable Enable
Bit 6
Gain1 Gain1 Gain1 Gain1 Gain1 Gain1 Gain1 Gain1 Gain1
Bit5
Gain0 Gain0 Gain0 Gain0 Gain0 Gain0 Gain0 Gain0 Gain0
Bit4(1)
IN4 IN4 IN4 IN4 IN4 IN4 IN4 IN4 IN4
Bit3
IN3 IN3 IN3 IN3 IN3 IN3 IN3 IN3 IN3
Bit2
IN2 IN2 IN2 IN2 IN2 IN2 IN2 IN2 IN2
Bit1
IN1 IN1 IN1 IN1 IN1 IN1 IN1 IN1 IN1
Bit0
IN0 IN0 IN0 IN0 IN0 IN0 IN0 IN0 IN0
Notes: 1. IN4 is provided for forward compatibility and should always be written as `0' in the FMS6501.
Clamp Control Register Contents and Defaults Control Name
Clmp
Width
1 bit
Type
Write
Default
0
Bit(s)
7:0
Description
Clamp / Bias selection: 1 = Clamp, 0 = Bias
Clamp Control Register Map Register Name
CLAMP1 CLAMP2
Register Address
0x1D 0x1E
Bit 7
Clmp8 Resv'd
Bit 6
Clmp7 Resv'd
Bit5
Clmp6 Resv'd
Bit4
Clmp5 Resv'd
Bit3
Clmp4 Clmp12
Bit2
Clmp3 Clmp11
Bit1
Clmp2 Clmp10
Bit0
Clmp1 Clmp9
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
www.fairchildsemi.com 5
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
DC Electrical Characteristics
TA = 25C, Vcc = 5V, VIN = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC coupled with 0.1F, unused inputs AC-terminated through 75 to GND, all outputs AC coupled with 220F into 150 loads, referenced to 400kHz, unless otherwise noted. Symbol
ICC VOUT ROFF Vclamp Vbias PSRR
Parameter
Supply Current1 Video Output Range Off Channel Output Impedance DC Output Level
1
Conditions
No load, all outputs enabled Output disabled Clamp mode Bias mode All channels, DC
Min.
Typ.
80 2.8 3.0
Max
100
Units
mA Vpp k
0.2 1.15
0.3 1.25 50
0.4 1.35
V V dB
DC Output Level1 Power Supply Rejection Ratio
Notes: 1. 100% tested at 25C.
AC Electrical Characteristics
TA = 25C, VCC = 5V, VIN = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC coupled with 0.1F, unused inputs AC-terminated through 75 to GND, all outputs AC coupled with 220F into 150 loads, referenced to 400kHz, unless otherwise noted. Symbol
AVSD AVSTEP f+1dB f-1dB fC dG dP THDSD THDHD XTALK1 XTALK2 XTALK3 XTALK4 XTALK5 SNRSD VNOISE AMPON Gain
Parameter
Channel Gain(1) Error Step(1)
Conditions
All Channels, All Gain Settings, DC All Channels, DC VOUT = 1.4Vpp VOUT = 1.4Vpp VOUT = 1.4Vpp 3.58MHz 3.58MHz VOUT = 1.4Vpp, 5MHz VOUT = 1.4Vpp, 22MHz 1MHz, VOUT = 2Vpp(2) 15MHz, VOUT = 2Vpp(2) 1MHz, VOUT = 2Vpp(3) 15MHz, VOUT = 2Vpp(3) Standard Video, VOUT = 2Vpp
(4)
Min.
-0.2 0.9
Typ.
0 1.0 65 90 115 0.1 0.2 0.05 0.6 -72 -50 -68 -61 -45 73 20 300
Max
+0.2 1.1
Units
dB dB MHz MHz MHz % deg % % dB dB dB dB dB dB nV/rtHz ns
1dB Peaking Bandwidth -1dB Bandwidth -3dB Bandwidth Differential Gain Differential Phase SD Output Distortion HD Output Distortion Input Crosstalk Input Crosstalk Output Crosstalk Output Crosstalk Multi-Channel Crosstalk Signal-to-Noise Channel Noise Amplifier Recovery Time Ratio(5)
NTC-7 Weighting, 4.2MHz LP, 100kHz HP 400kHz to 100MHz, Input Referred Post I 2C Programming
Notes: 1. 100% tested at 25C. 2. Adjacent input pair to adjacent output pair. Interfering input is through an open switch. 3. Adjacent input pair to adjacent output pair. Interfering input is through a closed switch. 4. Crosstalk of eight synchronous switching outputs onto single, asynchronous switching output. 5. Signal-to-Noise Ration (SNR) = 20 * log (714mV / rms noise).
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
www.fairchildsemi.com 6
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
I2C BUS Characteristics
TA = 25C and VCC = 5V unless otherwise noted. Symbol
Vil Vih fscl tr tf tlow thigh tSU,DAT tHD,DAT tSU,STO tBUF tHD,STA tSU,STA Digital Input Low Digital Input High Clock Frequency Input Rise Time Input Fall Time Clock Low Period Clock High Period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time Following a Stop Start Hold Time Start Set-up Time Following Clock Low to High
Parameter
(1) (1)
Conditions
SDA, SCL, ADDR SDA, SCL, ADDR SCK 1.5V to 3V 1.5V to 3V
Min.
0 3.0
Typ.
Max
1.5 Vcc
Units
V V kHz ns ns s s ns ns s s s s
100 1000 300 4.7 4.0 300 0 4 4.7 4 4.7
Notes: 1. 100% tested at 25C.
SDA
tBUF tLOW
tf
SCL
tHD,STA
tr
t HD,DAT
t HIGH
tSU,DAT
SDA
tSU,STA
tSU,STO
Figure 3. I2C Bus Timing
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
www.fairchildsemi.com 7
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
I2C Interface
Operation
The I2C-compatible interface conforms to the I2C specification for Standard Mode. Individual addresses may be written. There is no read capability. The interface consists of two lines. These is a serial data line (SDA) and a serial clock line (SCL), both of which must be connected to a positive supply through an external resistor. Data transfer may be initiated only when the bus is not busy.
Bit Transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the line during this time are interpreted as a control signal.
SCL
SDA
Data line stable; data valid
Change of data allowed
Figure 4. Bit Transfer
Start and Stop Conditions
The data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as START condition (S). A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as STOP condition (P).
SCL
S
P
SDA START condition STOP condition
Figure 5. Definition of START and STOP conditions
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
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FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Acknowledge
The data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a high-level signal put on the bus by the transmitter, during which the master generates an extra acknowledge-related clock pulse. A slave receiver must generate an acknowledge after the reception of each byte. A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
START condition
clock pulse for acknowledgement
SCL FROM MASTER
1
2
8
9
DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER
Figure 6. Acknowledgement on the I2C Bus
I2C Bus Protocol
Before any data is transmitted on the I2C bus, the device that should respond is addressed first. The addressing is always carried out with the first byte transmitted after the
1 SCL
start procedure. The I2C bus configuration for a data write to the FMS6501 is shown in Figure 5.
9
1
9
SDA
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY FMS6501
D7
D6
D5
D4
D3
D2
D1
D0
START BY MASTER
FRAME1 SERIAL BUS ADDRESS BYTE
ACK. BY FMS6501 FRAME 2 ADDRESS POINTER REGISTER BYTE 9
1 SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY FMS6501 STOP BY MASTER
FRAME 3 DATA BYTE
Figure 7. Write a Register Address to the Pointer Register, Then Write Data to the Selected Register
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
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FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Applications Information
Input Clamp / Bias Circuitry
The FMS6501 accommodates AC- or DC-coupled inputs. Internal clamping and bias circuitry are provided to support AC-coupled inputs. These are selectable through the CLMP bits via the I2C compatible interface. For DC-coupled inputs, the device should be programmed to use the 'bias' input configuration. In this configuration, the input is internally biased to 625mV through a 100k resistor. Distortion is optimized with the output levels set between 250mV above ground and 500mV below the power supply. These constraints, along with the desired channel gain, need to be considered when configuring the input signal levels for input DC coupling. With AC-coupled inputs, the FMS6501 uses a simple clamp rather than a full DC-restore circuit. For video signals with and without sync (Y,CV,R,G,B), the lowest voltage at the output pins is clamped to approximately 300mV above ground when the 6dB gain setting is selected. If symmetric AC-coupled input signals are used (chroma,Pb,Pr,Cb,Cr), the bias circuit described above can be used to center them within the input common range. The average DC value at the output is approximately 1.27V with a 6dB gain setting. This value changes depending upon the selected gain setting.
Video source must be AC-coupled
75
Figure 9 shows the bias mode input circuit and internally controlled voltage at the input pin for AC-coupled inputs.
Lowest voltage set to 625mV
0.1F
FMS6501 Input Bias
Figure 9. Bias Mode Input Circuit
Output Configuration
The FMS6501 outputs may be either AC or DC coupled. Resistive output loads can be as low as 75, representing a dual, doubly terminated video load. High impedance, capacitive loads up to 20pF can also be driven without loss of signal integrity. For standard 75 video loads, a 75 matching resistor should be placed in series to allow for a doubly terminated load. DC-coupled outputs should be connected as shown in Figure 10.
75
Gain Setting
6dB 7dB 8dB 9dB
Clamp Voltage
300mV 330mV 370mV 420mV
Bias Voltage
1.27V 1.43V 1.60V 1.80V
FMS6501 Output Amplifier
75
Figure 10. DC-Coupled Load Connection If multiple low-impedance loads are DC coupled, increased power and thermal issues need to be addressed. In this case, the use of a multilayer board with a large ground plane to help dissipate heat is recommended. If a two-layer board is used under these conditions, an extended ground plane directly under the device is recommended. This plane should extend at least 0.5 inches beyond the device. PC board layout issues are covered in the Layout Considerations section. AC-coupled loads should be configured as in Figure 11:
220F
Figure 8 shows the clamp mode input circuit and the internally controlled voltage at the input pin for AC-coupled inputs.
Lowest voltage set to 125mV
Video source must be AC-coupled
75
0.1F
FMS6501 Input Clamp
Figure 8. Clamp Mode Input Circuit
FMS6501 Output Amplifier
75
75
Figure 11. AC-Coupled Load Connection
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
www.fairchildsemi.com 10
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Thermal issues are significantly reduced with AC-coupled outputs, alleviating special PC layout requirements. Each of the outputs can be independently powered down and placed in a high-impedance state with the ENABLE bit. This function can be used to mute video signals, to parallel multiple FMS6501 outputs, or to save power. When the output amplifier is disabled, the high-impedance output presents a 3k load to ground. The output amplifier typically enters and recovers from the powerdown state in less than 300ns after being programmed. When an output channel is not connected to an input, the input to that channel's amplifier is forced to approximately 150mV. The output amplifier is still active unless specifically disabled by the I2C interface. Voltage output levels depend on the programmed gain for that channel.
For input crosstalk, the switch is open. All inputs are in bias mode. Channel 1 input is driven with a 1Vpp signal, while all other inputs are AC terminated with 75. All outputs are enabled and crosstalk is measured from IN1 to any output. For output crosstalk, the switch is closed. Crosstalk from OUT1 to any output is measured. Crosstalk from multiple sources into a given channel was measured with the setup shown in Figure 6. Input IN1 is driven with a 1Vpp pulse source and is connected to outputs Out1 to Out8. Input In9 is driven with a secondary, asynchronous, gray-field video signal, and is connected to Out9. All other inputs are AC terminated with 75. Crosstalk effects on the gray field are measured and calculated with respect to a standard 1Vpp output measured at the load. If not all inputs and outputs are needed, avoid using adjacent channels, where possible, to reduce crosstalk. Disable all unused channels to further reduce crosstalk and power dissipation.
TERMINATION Bias IN1 IN1 driven with SD videio 1Vpp IN9 driven with asynchronous SD video 1Vpp IN2-8 + IN10-12 driven with AC term to GND with 75 IN9 Bias
Crosstalk
Crosstalk is an important consideration when using the FMS6501. Input and output crosstalk are defined to represent the two major coupling modes in a typical application. Input crosstalk is crosstalk in the input pins and switches when the interfering signal drives an open switch. It is dominated by inductive coupling in the package lead frame between adjacent leads. It decreases rapidly as the interfering signal moves farther away from the pin adjacent to the input signal selected. Output crosstalk is coupling from one driven output to another active output. It decreases with increasing load impedance, as it is caused mainly by ground and power coupling between output amplifiers. If a signal is driving an open switch, its crosstalk is mainly input crosstalk. If it is driving a load through an active output, its crosstalk is mainly output crosstalk. Input and output crosstalk measurements are performed with the test configuration shown in Figure 12.
TERMINATION Bias IN1
IN12
Bias
Gain = 6dB OUT1 = 2.0Vpp
Measure crosstalk from Channels 1-8 into Channel 9 OUT1 OUT9
IN2 - IN12 are AC-Term to ground with 75 IN1 = 1Vpp Open switch for input crosstalk Close switch for output crosstalk
Figure 13. Test Configuration for Multi-Channel Crosstalk
IN12
Bias
Gain = 6dB OUT1 = 2.0Vpp
Input crosstalk from IN1 to OUTx OUT1 Output crosstalk from OUT1 to OUTx OUT9
Figure 12. Test Configuration for Crosstalk
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
www.fairchildsemi.com 11
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Layout Considerations
General layout and supply bypassing play major roles in high-frequency performance and thermal characteristics. Fairchild offers a demonstration board, FMS6501DEMO, to use as a guide for layout and to aid in device testing and characterization. The FMS6501DEMO is a 4-layer board with a full power and ground plane. For optimum results, follow the steps below as a basis for high frequency layout.
Include 10F and 0.1F bypass capacitors. Place the 10F capacitor within 0.75 inches of the
FMS6501 Video Switch Matrix Applications
The increased demand for consumer multimedia systems has created a challenge for system designers to provide cost-effective solutions to capitalize on the growth potential in graphics display technologies. These applications requires cost-effective video switching and filtering solutions to deploy high-quality display technologies rapidly and effectively to the target audience. Areas of specific interest include HDTV, media centers, and automotive "infotainment" (includes navigation, in-cabin entertainment, and back-up camera). In all cases, the advantages an integrated video switch matrix provides are high quality video switching specific to the application, as well as video input clamps and on-chip, lowimpedance output cable drivers with switchable gain. Generally the largest application for a video switch is for the front end of an HDTV, where it takes multiple inputs and routes them to appropriate signal paths (main picture and picture in picture - PiP). These are normally routed into ADCs followed by decoders. There are many different technologies for HDTV; including LCD, Plasma, and CRT, with similar analog switching circuitry. An example of a HDTV application is shown in Figure 14. This system combines a video switch matrix and two three-channel switchable anti-aliasing filters. There are two three-channel signal paths in the system; one for the main picture, the other for "Picture in Picture" (PiP).
power pin.
Place the 0.1F capacitor within 0.1 inches of the
power pin.
Connect all external ground pins as tightly as possible,
preferably with a large ground plane under the package. Layout channel connections to reduce mutual trace inductance. Minimize all trace lengths to reduce series inductances. If routing across a board, place device such that longer traces are at the inputs rather than the outputs. If using multiple, low-impedance, DC-coupled outputs, special layout techniques may be employed to help dissipate heat. If a multilayer board is used, a large ground plane directly under the device helps reduce package case temperature. For dual-layer boards, an extended plane can be used. Worst-case, additional die power due to DC loading can be estimated at (Vcc2/4Rload) per output channel. This assumes a constant DC output voltage of Vcc/2. For 5V Vcc with a dual-DC video load, add 25/(4*75) = 83mW, per channel.
VIPDEMOTM Control Software
The FMS6501 is configured via an I2C-compatible digital interface. To facilitate demonstration, Fairchild Semiconductor had developed the VIPDEMOTM GUI-based control software to write to the FMS6501 register map. This software is included in the FMS6501DEMO kit. Also included is a parallel port I2C adapter and an interface cable to connect to the demo board. Besides using the full FMS6501 interface, the VIPDEMOTM can also be used to control single-register read and writes for I2C.
Antenna CATV / Satellite
RF/Tuner
CVBS Main Picture FMS6501 Video Switch Matrix FMS6407 AntiAliasing Filter
Video Decoder Controller Chip Scaling Engine PCI Interface
CVBS
3
3
ADC
LVDS (Tx)
LVDS (Rx)
S-Video 1
2 2
S-Video 2
LCD Display
YPrPb (SD)
3 3 3 FMS6407 AntiAliasing Filter 3
Picture in Picture ADC
Video Decoder
YPrPb (HD)
Figure 14. HDTV Application using the FMS6501 Video Switch Matrix
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
www.fairchildsemi.com 12
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
SSOP-28
Figure 15. FMS6501 28-Lead Small Scale Outline Package (SSOP)
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
www.fairchildsemi.com 13
FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
www.fairchildsemi.com
(c) 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.2
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